1. Field of the Invention
The present invention relates to a semiconductor device for use as a switching transistor, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
There has heretofore been a semiconductor device in the form of a field-effect transistor (hereinafter referred to as an "FET") having p.sup.+ - and n.sup.+ -type regions formed in the surface of a p- or n-type semiconductor substrate. In the semiconductor device, a source region of the FET and a power supply electrode are generally connected to each other by an interconnection electrode. If the interconnection electrode and the power supply electrode are integrally formed with each other, then it is necessary to form a contact between the interconnection electrode and the source region. If the interconnection electrode and the source region are integrally formed with each other, then it is necessary to form a contact between the interconnection electrode and the power supply electrode. These contacts are not preferable because they would lower the productivity of semiconductor devices and increase the area of the surface of the semiconductor device.
A semiconductor device has been proposed in an attempt to solve the above problems, as disclosed in Japanese laid-open patent publication No. 2-283062. The disclosed semiconductor device will be described below with reference to FIGS. 1a and 1b of the accompanying drawings. FIGS. 1a and 1b show a structure of a CMOS (Complementary Metal Oxide Semiconductor) circuit as a semiconductor device. FIG. 1a is a plan view of the CMOS circuit, and FIG. 1b is a cross-sectional view taken along line A--A.
The CMOS circuit is formed on an n-type substrate 1 with a p-type well 2 in a surface thereof. The CMOS circuit includes a p-channel MOSFET 3 on the n-type substrate 1 and an n-channel MOSFET 4 on the p-type well 2.
An insulating layer 5 is disposed on the surface of the n-type substrate 1, and power supply electrodes 6, 7 of a metal such as aluminum are disposed respectively on opposite sides of the surface of the insulating layer 5. The power supply electrode 6 is connected to a positive terminal of a power supply (not shown), and the power supply electrode 7 is connected to ground.
An n.sup.+ -type conduction layer 8 is disposed in the surface of the n-type substrate 1, and the power supply electrode 6 is connected to the n.sup.+ -type conduction layer 8 through a through hole 9 defined in the insulating layer 5. Similarly, a p.sup.+ -type conduction layer 10 is disposed in the surface of the p-type well 2, and the power supply electrode 7 is connected to the p.sup.+ -type conduction layer 10 through a through hole 11 defined in the insulating layer 5.
A p.sup.+ -type source region 12 is disposed in the surface of the n-type substrate 1, and an n.sup.+ -type dielectric layer 13 is disposed adjacent to the p.sup.+ -type source region 12 in the surface of the n-type substrate 1. Likewise, an n.sup.+ -type source region 14 is disposed in the surface of the p-type well 2, and a p.sup.+ -type dielectric layer 15 is disposed adjacent to the n+-type source region 14 in the surface of the p-type well 2.
A through hole 16 defined in the insulating layer 5 extends to the surfaces of the source region 12 and the dielectric layer 13. A conductive layer 17 made of a metal such as aluminum is disposed on the surface of the insulating layer 5 and connected through the through hole 16 to the surfaces of the source region 12 and the dielectric layer 13.
Similarly, a through hole 18 defined in the insulating layer 5 extends to the surfaces of the source region 14 and the dielectric layer 15. A conductive layer 19 made of a metal such as aluminum is disposed on the surface of the insulating layer 5 and connected through the through hole 18 to the surfaces of the source region 14 and the dielectric layer 15.
An U-shaped gate electrode 20 made of a metal such as aluminum is disposed on the surface of the insulating layer 5 and extends from a position confronting the source region 12 to a position confronting the source region 14. A p.sup.+ -type drain region 21 is disposed in the surface of the n-type substrate 1 at a position confronting the gate electrode 20, and an n.sup.+ -type drain region 22 is disposed in the surface of the p-type well 2 at a position confronting the gate electrode 20.
An output electrode 23 of a metal such as aluminum is disposed on the surface of the insulating layer 5, and connected to the drain regions 21, 22 through a pair of through holes 24, 25 that are defined in the insulating layer 5. The output electrode 23 has an output terminal. Actually, the above structure of the CMOS circuit is covered with a protective layer (not shown) deposited on the uppermost surface thereof.
The p-channel MOSFET 3 comprises the gate electrode 20, the source region 12, and the drain region 21, and the n-channel MOSFET 4 comprises the gate electrode 20, the source region 14, and the drain region 22.
In the above CMOS circuit, the source region 12 of the p-channel MOSFET 3 is maintained at a positive potential applied from the power supply electrode 6, and the source region 13 of the n-channel MOSFET 4 is maintained at a ground potential by the power supply electrode 7 which is grounded.
Specifically, the potential applied from the power supply electrode 6 is conducted from the n.sup.+ -type conduction layer 8 connected thereto through the n-type substrate 1 to the n.sup.+ -type dielectric layer 13, from which the potential is conducted through the conductive layer 17 to the source region 12. Similarly, the ground potential from the power supply electrode 7 is conducted from the p.sup.+ -type conduction layer 10 connected thereto through the p-type well 2 to the p.sup.+ -type dielectric layer 15, from which the ground potential is conducted through the conductive layer 19 to the source region 14.
In the above CMOS circuit, therefore, the n.sup.+ - and p.sup.+ -type conduction layers 8, 10 are connected to the power supply electrodes 6, 7, and the n.sup.+ - and p.sup.+ -type dielectric layers 13, 15 are connected to the source regions 12, 14 by the conductive layers 17, 19 to keep the source regions 12, 14 and the power supply electrodes 6, 7 in a mutual conduction relationship without separate interconnections therebetween. Therefore, the power supply electrodes 6, 7 can freely be changed in position, and interconnections may be laid intermediate between the power supply electrodes 6, 7 and the conductive layers 17, 19.
A process of manufacturing the conventional CMOS circuit described above will briefly be described below by way of example. First, an n-type substrate 1 is prepared, and a p-type well 2 is formed in a surface thereof. Then, an n.sup.+ -type conduction layer 8, an n.sup.+ -type dielectric layer 13, a p.sup.+ -type source region 12, and a p.sup.+ -type drain region 21 are formed in another surface of the n-type substrate 1. A p.sup.+ -type conduction layer 10, a p.sup.+ -type dielectric layer 15, an n.sup.+ -type source region 14, and an n.sup.+ -type drain region 22 are formed in a surface of the p-type well 2.
Thereafter, an insulating layer 5 is uniformly deposited on the surface formed thus far on the n-type substrate 1. A through hole 9 reaching the surface of the conduction layer 8, a through hole 11 reaching the surface of the conduction layer 10, a through hole 16 reaching the common surface of the source region 12 and the dielectric layer 13, a through hole 18 reaching the common surface of the source region 14 and the dielectric layer 15, a through hole 24 reaching the surface of the drain region 21, and a through hole 25 reaching the surface of the drain region 22 are formed in the insulating layer 5.
Then, power supply electrodes 6, 7, conductive layers 17, 19, a gate electrode 20, and an output electrode 23, each made of a metal such as aluminum or the like, are formed on the surface of the insulating layer 5. The power supply electrode 6 is connected to the conduction layer 8 through the through hole 9, and the power supply electrode 7 is connected to the conduction layer 10 through the through hole 11. The source region 12 and the dielectric layer 13 are connected to the conductive layer 17 through the through hole 16, and the source region 14 and the dielectric layer 15 are connected to the conductive layer 19 through the through hole 18. The drain regions 21, 22 are connected to the output electrode 23 through the through holes 24, 25.
Because the conduction layers 8, 10 and the dielectric layers 13, 15 are connected respectively to the power supply electrodes 6, 7 and the source regions 12, 14, the power supply electrodes 6, 7 and the source regions 12, 14 are kept in a mutual conduction relationship without separate interconnections therebetween.
However, the conductive layers 17, 19 are required to connect the n.sup.+ - and p.sup.+ -type dielectric layers 13, 15 to the p.sup.+ - and n.sup.+ -type source regions 12, 14, and the through holes 16, 18 need to be formed in the insulating layer 5 in order to connect the conductive layers 17, 19 to the source regions 12, 14 and the dielectric layers 13, 15. These requirements make the productivity of the CMOS circuit relatively low.
While the output electrode 23 is connected to the drain regions 21, 22 through the through holes 24, 25, good conductivity can not be achieved by a single-point contact of the output electrode 23 with each of the drain regions 21, 22 because the drain regions 21, 22, comprising p.sup.+ - and n.sup.+ -type diffused layers, are of high resistance. One solution would be to make a number of through holes in the insulating layer 5 to increase the number of contacts of the output electrode 23 with the drain regions 21, 22. Such a solution would not be preferable because the productivity of the conventional CMOS circuit would be greatly reduced.
Since it is difficult to gain good conductivity between the output electrode 23 and the drain regions 21, 22, high performance capabilities cannot be expected of the conventional CMOS circuit, and the productivity of the conventional CMOS circuit is poor because of many through holes required. Furthermore, inasmuch as the conductive layers 17, 19 are exposed in gaps between the power supply electrodes 6, 7 and the gate electrode 20 on the surface of the insulating layer 5, it is difficult to form interconnections across those gaps, and hence the conventional CMOS circuit has a relatively low degree of integration.